Executive recruitment company Monroe Consulting Group Philippines is recruiting on behalf of the world's largest supplier of semiconductor test equipment for logic, RF, analog, power, mixed-signal, and memory technologies and deliver test solutions to developers and manufacturers of a broad range of integrated circuits, packaged separately or integrated as cells in system-on-a-chip (SOC) devices. This job is based in Lapu-Lapu City, Cebu.
Job Summary:
Our partner client is looking for talented people, who share their passion and drive, to join their team. Their customers are the world's leading electronics companies and they depend on the company to help them get quality products to market. At the organization, they ride the wave of technological innovation every day. It's an exciting business! If being part of a global team is something that excites you, this company may be the place for you.
Duties & Responsibilities:
- Develops and maintain a FPGA/ASIC verification environment for major design platforms.
- Assist Hardware engineering team during integration phase by creating automated, constrained randomized test-benches and debug flow problems in order to narrow down the issue.
- Develops and own functional blocks to be used on multiple platforms in order to enable regression and re-use of code.
- Creates library simulation models and environments
- Creating bus functional reference models that represent circuits on PCB's.
- Help create verification plans and specific test cases
- Perform debugging using lab equipment
- Communicate and verify test coverage with the designers, and implement these in a timely and high-quality manner using System Verilog or Verilog.
Basic Qualifications & Skills:
- BS Electrical or Electronics Engineer
- With minimum of 3 to 5 years FPGA design experience from design requirements to synthesis and simulations is an advantage.
- Preferably with experience on design verification environment (Digital or Analog)
- With experience on below is an advantage:
- Functional Verification as well as constrained randomized verification.
- SoC of Xilinx, Intel
- System Verilog
- Bus Functional models
- Xilinx Vivado EDA tool, Intel Quartus Prime, Cadence Xcelium Logic Simulation
- UVM Environment Familiarity
